Parallel turbo decoding with non-uniform window sizes

Abstract

Turbo decoder circuit executes turbo decoding process, and to restore the frame of data symbol from the signal received, the frame of the data symbol includes the soft-decision-value of each data symbol of the frame.The data symbol of the frame is encoded with turbo encoder, the turbo encoder include it is each can by the top convolution coder and lower part convolution coder of grid representation and between top convolution coder and lower part convolution coder interleaved encoded data interleaver.Turbo decoder circuit includes clock, configurable lattice network, top decoder and lower part decoder for the soft-decision-value that interweaves.Each of upper and lower part decoder includes processing element, the processing element is configured as during a series of continuous clocks recycle, priori soft-decision-value related with data symbol is iteratively received from configurable lattice network, the priori soft-decision-value is associated with the window of integer continuous grids grade of possible path between top or the state of lower part convolution coder is indicated.Processing element executes parallel computation associated with the window using priori soft-decision-value, to generate corresponding extrinsic soft-decision-value related with data symbol.Configurable lattice network includes network controller circuit, the network controller circuit iteratively controls the configuration of configurable lattice network during continuous clock recycles, to provide priori soft-decision-value by interweaving by extrinsic soft-decision-value that lower part decoder provides for top decoder, and priori soft-decision-value is provided for lower part decoder by interweaving by extrinsic soft-decision-value that top decoder provides.The intertexture of the configurable lattice network execution of device control is network controlled according to predetermined scheduling, this provides priori soft-decision-value in the different circulations that one or more continuous clocks recycle, and provides the competition between different priori soft-decision-values to the same treatment element on top or lower part decoder to avoid during identical dock cycles.Therefore, processing element can have multiple grades of the window size including grid, and decoder is allowed to be configured with any number of processing element, so that decoder circuit becomes any parallel turbo decoder.

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Identifiers

ORCID for Rob Maunder: orcid.org/0000-0002-7944-2615

ORCID for Luping Xiang: orcid.org/0000-0003-1465-6708

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