Polar decoder with LLR-domain computation of f-function and g-function
Polar decoder with LLR-domain computation of f-function and g-function
A polar decoder kernal (111) is described. The polar decoder kernal (111) includes a processing unit (2201) having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR, (2202, 2203); a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit (2201) includes only a single two-input adder (2207) to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.
EP3639376A1
24 August 2022
Maunder, Rob
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Brejza, Matthew Felix
a761342e-e140-45a7-ad48-095a6628af17
Zhong, Shida
68341271-2339-4e05-b7fc-ec6cbb22c1b3
Perez Andrade, Isaac
51aa4dad-b027-4b31-8cf7-1225889be1dc
Chen, Taihai
c5107a09-2235-4adf-b71b-c1e4a3534732
Maunder, Rob, Brejza, Matthew Felix, Zhong, Shida, Perez Andrade, Isaac and Chen, Taihai
(Inventors)
(2022)
Polar decoder with LLR-domain computation of f-function and g-function.
EP3639376A1.
Abstract
A polar decoder kernal (111) is described. The polar decoder kernal (111) includes a processing unit (2201) having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR, (2202, 2203); a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit (2201) includes only a single two-input adder (2207) to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.
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Published date: 24 August 2022
Identifiers
Local EPrints ID: 473952
URI: http://eprints.soton.ac.uk/id/eprint/473952
PURE UUID: 84dd8abe-46a3-430b-8fb3-425b89291a30
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Date deposited: 06 Feb 2023 17:42
Last modified: 17 Mar 2024 03:14
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Contributors
Inventor:
Rob Maunder
Inventor:
Matthew Felix Brejza
Inventor:
Shida Zhong
Inventor:
Isaac Perez Andrade
Inventor:
Taihai Chen
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