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Polar coder with logical three-dimensional memory, communicaton unit, integrated circuit and method therefor

Polar coder with logical three-dimensional memory, communicaton unit, integrated circuit and method therefor
Polar coder with logical three-dimensional memory, communicaton unit, integrated circuit and method therefor
A polar coder circuit is described. The polar coder circuit comprises one or more datapaths; and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising a number of one or more random access memories, RAMs, of the logical 3D memory block as a first dimension, wherein the one or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size 2sd, where sd is a number of stages in a datapath of the one or more datapaths.
US11146294B2
Maunder, Rob
76099323-7d58-4732-a98f-22a662ccba6c
Brejza, Matthew Felix
a761342e-e140-45a7-ad48-095a6628af17
Zhong, Shida
68341271-2339-4e05-b7fc-ec6cbb22c1b3
Perez Andrade, Isaac
51aa4dad-b027-4b31-8cf7-1225889be1dc
Chen, Taihai
c5107a09-2235-4adf-b71b-c1e4a3534732

Maunder, Rob, Brejza, Matthew Felix, Zhong, Shida, Perez Andrade, Isaac and Chen, Taihai (Inventors) (2021) Polar coder with logical three-dimensional memory, communicaton unit, integrated circuit and method therefor. US11146294B2.

Record type: Patent

Abstract

A polar coder circuit is described. The polar coder circuit comprises one or more datapaths; and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising a number of one or more random access memories, RAMs, of the logical 3D memory block as a first dimension, wherein the one or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size 2sd, where sd is a number of stages in a datapath of the one or more datapaths.

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US11146294 - Version of Record
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Published date: 12 October 2021

Identifiers

Local EPrints ID: 473957
URI: http://eprints.soton.ac.uk/id/eprint/473957
PURE UUID: 8aca67dd-8456-4423-a945-940449bc570e
ORCID for Rob Maunder: ORCID iD orcid.org/0000-0002-7944-2615

Catalogue record

Date deposited: 06 Feb 2023 17:44
Last modified: 17 Mar 2024 03:14

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Contributors

Inventor: Rob Maunder ORCID iD
Inventor: Matthew Felix Brejza
Inventor: Shida Zhong
Inventor: Isaac Perez Andrade
Inventor: Taihai Chen

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