Maunder, Rob, Brejza, Matthew Felix, Zhong, Shida, Perez Andrade, Isaac and Chen, Taihai (Inventors) (2022) Block-wise parallel freezing bit generation for polar code. KR20200066606A.
Record type:
Patent
More information
Published date: 12 April 2022
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Identifiers
Local EPrints ID: 474012
URI: http://eprints.soton.ac.uk/id/eprint/474012
PURE UUID: 64f618f7-a5ca-4fdf-b88d-6a1e62dd1759
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Date deposited: 08 Feb 2023 18:01
Last modified: 17 Mar 2024 03:14
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Contributors
Inventor:
Rob Maunder
Inventor:
Matthew Felix Brejza
Inventor:
Shida Zhong
Inventor:
Isaac Perez Andrade
Inventor:
Taihai Chen
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