A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits
A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits
RMS AC supply current monitoring with the addition of the novel DFT technique presented in this paper shows an increase in fault coverage for an embedded opamp from only 2.5% to over 70%. During a test, the effective width- length ratio of the transistors that draw the most AC current is reduced, causing the supply current drawn by other parts of the circuit that might be faulty to contribute relatively more to the overall supply current, allowing detection of faults. The results of Monte Carlo fault simulations demonstrate the principle. The most significant advantages of this DFT technique are increased fault coverage; small (1%) area overhead; and low impact on the performance of the circuit.
9/1-9/5
Chalk, C. D.
cf6e3a0d-3bc0-4ee9-9ab7-d82b0f518ced
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Wilkins, B. R.
b7b6acfe-93b9-4d4a-a5ac-b52438ab26ca
1997
Chalk, C. D.
cf6e3a0d-3bc0-4ee9-9ab7-d82b0f518ced
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Wilkins, B. R.
b7b6acfe-93b9-4d4a-a5ac-b52438ab26ca
Chalk, C. D., Zwolinski, M. and Wilkins, B. R.
(1997)
A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits.
IEE Colloquium (Digest), (361), .
Abstract
RMS AC supply current monitoring with the addition of the novel DFT technique presented in this paper shows an increase in fault coverage for an embedded opamp from only 2.5% to over 70%. During a test, the effective width- length ratio of the transistors that draw the most AC current is reduced, causing the supply current drawn by other parts of the circuit that might be faulty to contribute relatively more to the overall supply current, allowing detection of faults. The results of Monte Carlo fault simulations demonstrate the principle. The most significant advantages of this DFT technique are increased fault coverage; small (1%) area overhead; and low impact on the performance of the circuit.
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Published date: 1997
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Local EPrints ID: 475874
URI: http://eprints.soton.ac.uk/id/eprint/475874
ISSN: 0963-3308
PURE UUID: 8b80019c-6c40-4d3d-8646-1f3ce41a7b1b
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Date deposited: 29 Mar 2023 16:47
Last modified: 06 Jun 2024 01:32
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Author:
C. D. Chalk
Author:
M. Zwolinski
Author:
B. R. Wilkins
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