Design for test technique for increasing the resolution of supply current monitoring in analogue circuits
Design for test technique for increasing the resolution of supply current monitoring in analogue circuits
A design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty.
Circuit testing, Design for testability
1746-1748
Chalk, C. D.
cf6e3a0d-3bc0-4ee9-9ab7-d82b0f518ced
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
9 October 1997
Chalk, C. D.
cf6e3a0d-3bc0-4ee9-9ab7-d82b0f518ced
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Chalk, C. D. and Zwolinski, M.
(1997)
Design for test technique for increasing the resolution of supply current monitoring in analogue circuits.
Electronics Letters, 33 (21), .
(doi:10.1049/el:19971174).
Abstract
A design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty.
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Published date: 9 October 1997
Keywords:
Circuit testing, Design for testability
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Local EPrints ID: 476338
URI: http://eprints.soton.ac.uk/id/eprint/476338
ISSN: 0013-5194
PURE UUID: 4650369f-a87d-489c-9f52-7b8e51cac50e
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Date deposited: 19 Apr 2023 16:46
Last modified: 17 Mar 2024 02:35
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Contributors
Author:
C. D. Chalk
Author:
M. Zwolinski
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