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A novel non-minimal turn model for highly adaptive routing in 2D NoCs

A novel non-minimal turn model for highly adaptive routing in 2D NoCs
A novel non-minimal turn model for highly adaptive routing in 2D NoCs

Network-on-Chip (NoC) is emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for future micro-architectures (MPSoC and CMP). One of current issue in NoC routing is the use of acyclic channel dependency graph (ACDG) for deadlock freedom prohibiting certain routing turns. Thus, ACDG reduces the degree of adaptiveness. In this paper, we propose a novel nonminimal turn model which allows cycles in channel dependency graph provided that extended channel dependency graph is acyclic. Proposed turn model reduces number of restrictions on routing turns (specially on 90-degree), hence able to provide additional minimal and non-minimal routes between source and destination. We also propose a non-minimal and congestion-aware adaptive routing algorithm based on proposed turn model to demonstrate advantages. From results, we can observe that proposed method improves the network performance by distributing the traffic load in the non-congested regions.

deadlock freedom, Networks-on-Chip congestion, non-minimal paths, real traffic, routing
2324-8432
IEEE
Kumar, Manoj
4b3bfd7e-146c-4d0c-81d9-d1434061b9f8
Laxmi, Vijay
e79a9a3a-cd6b-45d6-8a03-9a5891453a95
Gaur, Manoj Singh
589ebe4b-7e06-4565-b109-8e268f8e12db
Daneshtalab, Masoud
600c11e6-1508-4487-be7d-b290272beb60
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Garcia, Lorena
Kumar, Manoj
4b3bfd7e-146c-4d0c-81d9-d1434061b9f8
Laxmi, Vijay
e79a9a3a-cd6b-45d6-8a03-9a5891453a95
Gaur, Manoj Singh
589ebe4b-7e06-4565-b109-8e268f8e12db
Daneshtalab, Masoud
600c11e6-1508-4487-be7d-b290272beb60
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Garcia, Lorena

Kumar, Manoj, Laxmi, Vijay, Gaur, Manoj Singh, Daneshtalab, Masoud and Zwolinski, Mark (2015) A novel non-minimal turn model for highly adaptive routing in 2D NoCs. Garcia, Lorena (ed.) In 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings. IEEE. 6 pp . (doi:10.1109/VLSI-SoC.2014.7004192).

Record type: Conference or Workshop Item (Paper)

Abstract

Network-on-Chip (NoC) is emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for future micro-architectures (MPSoC and CMP). One of current issue in NoC routing is the use of acyclic channel dependency graph (ACDG) for deadlock freedom prohibiting certain routing turns. Thus, ACDG reduces the degree of adaptiveness. In this paper, we propose a novel nonminimal turn model which allows cycles in channel dependency graph provided that extended channel dependency graph is acyclic. Proposed turn model reduces number of restrictions on routing turns (specially on 90-degree), hence able to provide additional minimal and non-minimal routes between source and destination. We also propose a non-minimal and congestion-aware adaptive routing algorithm based on proposed turn model to demonstrate advantages. From results, we can observe that proposed method improves the network performance by distributing the traffic load in the non-congested regions.

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More information

Published date: 7 January 2015
Venue - Dates: 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014, , Playa del Carmen, Mexico, 2014-10-06 - 2014-10-08
Keywords: deadlock freedom, Networks-on-Chip congestion, non-minimal paths, real traffic, routing

Identifiers

Local EPrints ID: 477978
URI: http://eprints.soton.ac.uk/id/eprint/477978
ISSN: 2324-8432
PURE UUID: 69f4e031-9f72-4985-9d47-5f9f91b40561
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 19 Jun 2023 16:38
Last modified: 17 Mar 2024 02:35

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Contributors

Author: Manoj Kumar
Author: Vijay Laxmi
Author: Manoj Singh Gaur
Author: Masoud Daneshtalab
Author: Mark Zwolinski ORCID iD
Editor: Lorena Garcia

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