Fault-orientated testing of MOS circuits

Abstract

It is widely accepted that the most efficient method of testing digital integrated circuits is to use a fault-orientated approach. Assumptions are made about the faults that can occur in a circuit, and the circuit is tested for the absence of these assumed faults. Over the last twenty years one set of assumptions - the stuck-at fault model – has emerged as being particularly suitable for testing digital circuits made from TTL SSI/MSI components mounted on a pcb. However, the stuck-at fault model is also routinely used to test state-of-the-art MOS VLSI circuits, despite the lack of evidence for its suitability for this task.
In this thesis, the appropriateness of the stuck-at fault model for MOS circuit testing is assessed by identifying the common NMOS failure modes, and by using the SPICE circuit simulator to determine their assoicated fault-effects, as well as by direct analysis of defective NMOS circuits. A switch-level fault model is proposed that more accurately reflects the common MOS faults, and a classical test pattern generation algorithm - the D-Algorithm - is modified using a branch of graph theory called path algebras to provide a new method of automatic test pattern generation. The method is shown to be readily extendable to CMOS circuits and some insights into "layout for testability" are given.

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