Network-on-chip: Current issues and challenges

Gaur, Manoj Singh, Laxmi, Vijay, Zwolinski, Mark, Kumar, Manoj, Gupta, Niyati and Ashish, (2015) Network-on-chip: Current issues and challenges. 19th International Symposium on VLSI Design and Test, VDAT 2015, , Ahmedabad, India. 26 - 29 Jun 2015. 3 pp . (doi:10.1109/ISVDAT.2015.7208160).

Abstract

Due to the shrinking transistor sizes, the density of ICs roughly doubles every year as predicted by Moore's law. These advancements in the VLSI integration densities towards the nano scale era, witnessed a paradigm shift from computation centric designs to communication centric designs incorporating very large number of simple cores. Plenty of traditional interconnect schemes like point to point, buses and crossbars are available to interconnect small number of cores. While achieving fast and efficient communication with point to point communication schemes, wire density is a barrier for adapting them to many core architectures. Moreover, buses are simpler in design, they suffer from the scalability and arbitration issues along with bandwidth bottleneck as the number of cores increases. Similarly area and power requirements of a crossbar limits its applicability. Hence, in many core architectures like Chip Multiprocessors (CMP) and Multi processor System-on-Chip (MPSoCs), emerge the need of an efficient communication infrastructure as traditional solutions fails to handle the communication challenges. Network-on-Chip (NoC), a scalable and modular design approach, has been proposed as a promising alternative to traditional bus based architectures for inter-core communication.

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Contributors

Author: Mark Zwolinski

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