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Mixed circuit logic level simulation

Mixed circuit logic level simulation
Mixed circuit logic level simulation
he design of a data or signal processing system is partitioned into analogue and digital modules according to the level of signal abstraction required. Interaction between analogue and digital modules of the circuit makes independent simulation of the modules less useful particularly when signals pass round closed loops incorporating both analogue and digital modules. Circuit level simulation of the whole system while accurate, is too costly and anyway circuit-level characterisation of digital modules is not always available. These considerations drive the development of mixed-mode simulators for logic level simulation, while less precise, in three to four orders of magnitude faster than circuit level simulation. The integration of a circuit simulator and a logic simulator into the same package, however, requires attention to details of interfacing, both of signals at different levels of abstraction and of time flow in the two simulators. These issues are the substance of this presentation.< >
Zwolinski, Mark
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Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Zwolinski, Mark (1993) Mixed circuit logic level simulation. 1993 IEEE International Symposium on Circuits and Systems, , Chicago, United States. 03 May - 06 Jul 1993. 4 pp .

Record type: Conference or Workshop Item (Paper)

Abstract

he design of a data or signal processing system is partitioned into analogue and digital modules according to the level of signal abstraction required. Interaction between analogue and digital modules of the circuit makes independent simulation of the modules less useful particularly when signals pass round closed loops incorporating both analogue and digital modules. Circuit level simulation of the whole system while accurate, is too costly and anyway circuit-level characterisation of digital modules is not always available. These considerations drive the development of mixed-mode simulators for logic level simulation, while less precise, in three to four orders of magnitude faster than circuit level simulation. The integration of a circuit simulator and a logic simulator into the same package, however, requires attention to details of interfacing, both of signals at different levels of abstraction and of time flow in the two simulators. These issues are the substance of this presentation.< >

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More information

Published date: 18 February 1993
Venue - Dates: 1993 IEEE International Symposium on Circuits and Systems, , Chicago, United States, 1993-05-03 - 1993-07-06

Identifiers

Local EPrints ID: 479737
URI: http://eprints.soton.ac.uk/id/eprint/479737
PURE UUID: e99bdd87-14a2-43dd-90c6-dcbb84454e10
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 26 Jul 2023 16:55
Last modified: 12 Jul 2024 01:32

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Author: Mark Zwolinski ORCID iD

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