A highly accurate spike sorting processor with reconfigurable embedded frames for unsupervised and adaptive analysis of neural signals
A highly accurate spike sorting processor with reconfigurable embedded frames for unsupervised and adaptive analysis of neural signals
Future implantable devices demand ultra-low power consumption with self-calibration capability providing real-time processing of biomedical signals. This paper introduces an adaptive processing framework for highly accurate on-chip spike sorting processing by learning the signal model in the recorded neural data. The novel adaptive spike sorting processor employs dual thresholding detection, adaptive feature extraction and online clustering with sorting threshold self-tuning capability. A prototype chip was fabricated in 180 nm CMOS technology. It achieves 84.5% overall clustering accuracy, provides up to 240X data reduction and consumes 148 μW of power from a 1.8 V supply voltage.
267-270
Zamani, Majid
431788cc-0702-4fa9-9709-f5777a2d0d25
Jiang, Dai
782f1637-d100-43dd-821f-6e4e156a50db
Demosthenous, Andreas
bed19531-d770-4f48-8464-59d225ddea8d
Zamani, Majid
431788cc-0702-4fa9-9709-f5777a2d0d25
Jiang, Dai
782f1637-d100-43dd-821f-6e4e156a50db
Demosthenous, Andreas
bed19531-d770-4f48-8464-59d225ddea8d
Zamani, Majid, Jiang, Dai and Demosthenous, Andreas
(2017)
A highly accurate spike sorting processor with reconfigurable embedded frames for unsupervised and adaptive analysis of neural signals.
In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.
IEEE.
.
(doi:10.1109/ESSCIRC.2017.8094577).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Future implantable devices demand ultra-low power consumption with self-calibration capability providing real-time processing of biomedical signals. This paper introduces an adaptive processing framework for highly accurate on-chip spike sorting processing by learning the signal model in the recorded neural data. The novel adaptive spike sorting processor employs dual thresholding detection, adaptive feature extraction and online clustering with sorting threshold self-tuning capability. A prototype chip was fabricated in 180 nm CMOS technology. It achieves 84.5% overall clustering accuracy, provides up to 240X data reduction and consumes 148 μW of power from a 1.8 V supply voltage.
This record has no associated files available for download.
More information
e-pub ahead of print date: 7 November 2017
Additional Information:
Publisher Copyright:
© 2017 IEEE.
Venue - Dates:
43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, , Leuven, Belgium, 2017-09-11 - 2017-09-14
Identifiers
Local EPrints ID: 489258
URI: http://eprints.soton.ac.uk/id/eprint/489258
PURE UUID: 92a005d6-9a99-4d10-a24f-d759d4d12f94
Catalogue record
Date deposited: 18 Apr 2024 16:48
Last modified: 19 Apr 2024 02:06
Export record
Altmetrics
Contributors
Author:
Majid Zamani
Author:
Dai Jiang
Author:
Andreas Demosthenous
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics