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SYNAPSE - a new approach to semi-automated design of ultra-low-power application-specific embedded processors

SYNAPSE - a new approach to semi-automated design of ultra-low-power application-specific embedded processors
SYNAPSE - a new approach to semi-automated design of ultra-low-power application-specific embedded processors
The main contribution of this paper is a new approach to semi-automated synthesis of Application Specific Embedded Processors (ASEPs). Designers of ASEPs do not have the comfort of standardized software support because the instruction sets are customised. Therefore, ASEP designs are frequently performed manually. However, in recent years a growing interest in ASEPs has been observed. This can be explained by the following two factors. Firstly, in contrast to general-purpose processors, ASEPs are particularly resilient to cybersecurity threats, which nowadays affect both software and hardware in modern SoC applications, especially in critical areas such as medicine, communication or smart grids. Secondly, the usual justification for using ASEP designs is their excellent performance and power efficiency characteristics which are comparable or can exceed those of dedicated hardware. Results presented in this paper show that automated ASEP designs can be more than an order of magnitude smaller, and therefore more power efficient, than equivalent general-purpose application-specific embedded processors. The small size results from the fact that both the architecture and instruction set of an ASEP are tailored to the unique needs of a particular application within the embedded system. The automation approach presented in this paper helps to reduce the high design costs and necessity to use highly skilled design engineers.
NIOS, RISC-V, application-specific embedded processors, automated digital synthesis, embedded systems, picoRISC, ultra-low power
135-139
IEEE
Ji, Xuan
3a65d964-5713-4f72-a9ca-fec551aba977
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Ji, Xuan
3a65d964-5713-4f72-a9ca-fec551aba977
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Ji, Xuan, Kazmierski, Tom J. and Halak, Basel (2025) SYNAPSE - a new approach to semi-automated design of ultra-low-power application-specific embedded processors. In the 32nd International Conference Mixed Design of Integrated Circuits and Systems (MIXDES). IEEE. pp. 135-139 . (doi:10.23919/MIXDES66264.2025.11091879).

Record type: Conference or Workshop Item (Paper)

Abstract

The main contribution of this paper is a new approach to semi-automated synthesis of Application Specific Embedded Processors (ASEPs). Designers of ASEPs do not have the comfort of standardized software support because the instruction sets are customised. Therefore, ASEP designs are frequently performed manually. However, in recent years a growing interest in ASEPs has been observed. This can be explained by the following two factors. Firstly, in contrast to general-purpose processors, ASEPs are particularly resilient to cybersecurity threats, which nowadays affect both software and hardware in modern SoC applications, especially in critical areas such as medicine, communication or smart grids. Secondly, the usual justification for using ASEP designs is their excellent performance and power efficiency characteristics which are comparable or can exceed those of dedicated hardware. Results presented in this paper show that automated ASEP designs can be more than an order of magnitude smaller, and therefore more power efficient, than equivalent general-purpose application-specific embedded processors. The small size results from the fact that both the architecture and instruction set of an ASEP are tailored to the unique needs of a particular application within the embedded system. The automation approach presented in this paper helps to reduce the high design costs and necessity to use highly skilled design engineers.

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More information

Published date: 30 April 2025
Keywords: NIOS, RISC-V, application-specific embedded processors, automated digital synthesis, embedded systems, picoRISC, ultra-low power

Identifiers

Local EPrints ID: 504848
URI: http://eprints.soton.ac.uk/id/eprint/504848
PURE UUID: 341ea1e3-ad5c-43bd-a084-e0903ee8a1be
ORCID for Xuan Ji: ORCID iD orcid.org/0009-0008-3968-7539
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 19 Sep 2025 16:41
Last modified: 27 Sep 2025 02:19

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Contributors

Author: Xuan Ji ORCID iD
Author: Tom J. Kazmierski
Author: Basel Halak ORCID iD

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