READ ME File For 'data.xlsx' Dataset DOI: 10.5258/SOTON/D3799 ReadMe Author: YUE ZHANG, University of Southampton ORCID ID : 0009-0002-9275-1989 This dataset supports the thesis entitled 'Advanced logic locking: a new strategy combining dynamic and zero-knowledge techniques' AWARDED BY: University of Southampton DATE OF AWARD: 2026 Date of data collection: 2026-01-29 -------------------- DATA & FILE OVERVIEW -------------------- This dataset contains: data.xlsx There are 5 different sheets in this file: Sheet_1 stores the source data of Table 3.2 in the thesis which presents time consumption to implement Zeki on different benchmarks. Sheet_2 stores the source data of Table 3.3 in the thesis which presents time consumption for SAT-solver (MiniSAT) to creak the key-bit of different benchmark circuits locked by RLL. Sheet_3 stores the source data of figure 3.11 in the thesis which presents percentage of pair-wise secured key-gate in benchmark circuits locked by Zeki and RLL. Sheet_4 stores the source data of figure 3.13 in the thesis which presents power overhead of DLL protected circuit with 64-bit and 128-bit key. Sheet_5 stores the source data of figure 3.13 in the thesis which presents area overhead of DLL protected circuit with 64-bit and 128-bit key. -------------------------- METHODOLOGICAL INFORMATION -------------------------- The experiments were carried out on a 8 core M1 Mac processor with 8Gb of RAM. Combinational benchmarks from EPFL, ISCAS and ITC99 suite were used in the experiment. The experiments were repeated for 10 times and average value of simulation result are used as data. All the work was done by myself. -------------------------- DATA-SPECIFIC INFORMATION -------------------------- Sheet_1 Variable list: Benchmark (Benchmark name), Input number, output number, gate number, Zeki running time (time consumption of implementing Zeki on selected benchmark in second) Sheet_2 Variable list: Benchmark (Benchmark name), gate number, SAT-solver Running Time (time consumption for SAT-solver (MiniSAT) to creak the key-bit of different benchmark circuits locked by RLL in second) Sheet_3 Each row represents percentage of pair-wise secured key-gate of different Benchmarks. Sheet_4 Variable list: Benchmark (Benchmark name), power overhead of 64-bit key protected benchmark, power overhead of 128-bit key protected benchmark Sheet_5 Variable list: Benchmark (Benchmark name), area overhead of 64-bit key protected benchmark, area overhead of 128-bit key protected benchmark Date that the file was created: 01, 2026