Design of a retentive and single-event upset tolerant TSPC flip-flop

Cirakoglu, Ahmet, Serb, Alex, Humood, Khaled, Zwolinski, Mark and Prodromakis, Themis (2025) Design of a retentive and single-event upset tolerant TSPC flip-flop. In 2025 32nd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2025. IEEE. 5 pp . (doi:10.1109/ICECS66544.2025.11270557).

Abstract

True single-phase-clock flip-flops (TSPC-FFs) offer a power- and area-efficient alternative to conventional master-slave (MS) flip-flops, making them well suited for high-speed and low-power digital designs. For instance, TSPC-FFs are suitable for improving the performance of novel deep neural network hardware accelerators. The benefits of TSPC-FF also meet the needs of space applications. However, a major disadvantage of TSPC-FF is data loss during the absence of a clock signal for an extended period, rendering energy-efficient schemes like clock-gating unfeasible. We propose a new single-event upset (SEU) tolerant TSPC-FF design that uniquely incorporates a hardened dual-inverter latch using C-elements that can be used for soft-error mitigation in normal operation and data retention during clock-gating. Post-layout simulations across process-voltage-temperature corners and Monte Carlo variations show that the proposed design achieves an approximately 4.5× higher minimum critical charge compared to a recent rad-hard reference design, which uses dual modular redundancy.

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Contributors

Author: Mark Zwolinski

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