Capacitor design for high-speed high-precision charge redistribution SAR ADCs

Abstract

Analog-to-Digital Converters (ADC) are a key component in the majority of instrumentation and imaging applications, and are often the limiting factor in their system performance. In the high-precision (>16b), high-speed (>100MHz) space, successive approximation register (SAR) based ADCs are favoured. These ADCs usually contain a capacitive DAC (CDAC) whose output is matched to the input signal through charge redistribution. The CDAC is built in the back-end-of-line (BEOL) layers of a typical CMOS process with the Cu metal tracks and low-k dielectric insulation forming lateral coupling capacitors. The resultant precision and performance of the CDAC SAR ADC is frequently limited by the errors developed during fabrication of the nominally identical capacitors in the CDAC.
Improving or correcting for the matching of the capacitors is an expensive, difficult, and time-consuming procedure. Improvement in the variation of capacitors is hard to achieve as both systematic and stochastic errors are introduced within the CMOS fabrication process. These processes are optimised for the performance of the underlying transistors and cannot be adjusted to benefit a BEOL capacitor array. Hence, typically, each capacitor on each die is measured after fabrication, followed by additional expensive calibration, supporting circuitry, and the implementation of power and time-consuming linearisation techniques to compensate for such variations.
This thesis investigates in detail the influence of the geometric design and circuit layout of the capacitor array on its matching properties in a 40nm CMOS process, with the aim of achieving improved matching performance of the DAC to minimise the requirement for additional supporting circuitry or calibration routines. This is achieved through the use of dedicated test chips designed and optimised for the measurement of the capacitors in large arrays, as well as development of an ultra-precise methodology for doing so. This has resulted in a significantly enhanced understanding of both the systematic and correlated errors in the process as well as the random error due to statistical variation. From this work three main conclusions are drawn.
Firstly, it is shown that variation in capacitive value scales inversely proportional to the square root of the length of the capacitor fingers and number of metal layers as would have been expected from a typical statistical (Pelgrom) model. However, it is also shown that the variation due to scaling of finger width and spacing, is primarily determined by the critical dimension of the process, and that matching is significantly improved through relaxing these parameters slightly. Together, these observations allow an optimised design which balances capacitor matching against area use.
Secondly, the measurement and analysis of the capacitor matching in three different 40 nm CMOS designs reveals that despite all care and attention in the layout design, a large part of the variation in capacitor values is derived from the most subtle limitations of process technology leading to unpredictable but systematic errors across the die which are repeated on all other die. This means that by careful separation of the matching errors into systematic index-to-index variations and random die-to-die variations, it is possible to compensate for the systematic errors by only measuring a very small subset of all available dies. This approach will lead to a significant time and cost saving in the test and calibration phase of each die.
Lastly, the research reveals that, due to the presence of correlated error sources, considerable matching improvements may be attained through proper understanding of the relationships between the key capacitor geometry parameters, and the aggressive use of layout folding schemes. Additional benefit can also be achieved through use of the correct amount, and type, of dummy structures on arrays of all sizes.
The developed theory and findings in the earlier sections are subsequently applied to a simulated model of a single-stage 18-bit SAR ADC, demonstrating that the capacitor mismatch error is now surpassed by noise as the dominant source of error in the system, and that the effectiveness of other linearisation techniques is also further enhanced by the optimised capacitor design.

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Identifiers

ORCID for William Christopher Webb: orcid.org/0000-0003-3568-6279

ORCID for Kees De Groot: orcid.org/0000-0002-3850-7101

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