An investigation of delay fault testing for multi voltage design

Abstract

Multi Voltage Design (MVD) has been successfully applied in contemporary processors as a technique to reduce energy consumption. This work is aimed at finding a generalised delay testing method for MVD. There has been little work to date on testing such systems, but testing the smallest number of operating voltages reduces testing costs. In the initial stage, the impact of varying supply voltage on different types of physical defects is analysed. Simulation results indicate that it is necessary to conduct test at more than one operating voltage and the lowest operating voltage does not necessarily give the best fault coverage. The second part of this work is related to the issues in the testing of level shifters in a MVD environment. The testing of level shifters was analysed to determine if high test coverage can be achieved at a single supply voltage. Resistive opens and shorts were considered and it was shown that, for testing purposes, consideration of purely digital fault effects is sufficient. Multiple faults were also considered. In all cases, it can be concluded that a single supply voltage is sufficient to test the level shifters. To further enhance the quality of test, we have proposed fault modelling and simulations using VHDL-AMS. Our simulation results show that the model derived using simplified VHDL-AMS gives acceptable results and significantly reduces the fault simulations time.

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ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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