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System level performance and yield optimisation for analogue integrated circuits

Md Ali, Sawal Hamid (2009) System level performance and yield optimisation for analogue integrated circuits University of Southampton, School of Electronics and Computer Science, Doctoral Thesis , 224pp.

Record type: Thesis (Doctoral)

Abstract

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield.
This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype.
For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse.
A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology.

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More information

Published date: November 2009
Organisations: University of Southampton

Identifiers

Local EPrints ID: 69724
URI: http://eprints.soton.ac.uk/id/eprint/69724
PURE UUID: ce1e6a8e-cfa0-419d-bba8-864f79cbb600

Catalogue record

Date deposited: 27 Nov 2009
Last modified: 19 Jul 2017 00:06

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Contributors

Author: Sawal Hamid Md Ali
Thesis advisor: Peter Wilson

University divisions

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