On-Chip time measurement architectures and implementation

Description/Abstract

In recent years, system on chip (SoC) devices have become increasingly popular in many applications, such as automotive, signal processing, portable electronic devices and communication products. This has led to more functionality being integrated onto a single piece of silicon. As the level of technology decreases down to smaller geometries, not only has the design become more complicated but also the verification of such devices has become significantly complex that it has led to stringent timing requirements being placed on such devices. With the continuing integration and speed scaling to higher frequencies into the low giga hertz range, limitations in the effectiveness of traditional production testing have been introduced. The increase in cost of automatic test equipment (ATE) and the fact that the electrical distance between the tester and the embedded core under test (CUT) has got wider has made the verification of such devices challenging.

To alleviate this cost test problem, this research investigates the design and methods associated with high resolution on-chip time measurement systems and proposes the design of a low cost, high resolution, programmable time measurement architecture for characterizing on-chip time measurements. This new architecture is based on the time-to-digital conversion (TDC) method and uses the dual-slope technique to perform the timing measurement. The proposed architecture can perform a number of different types of time measurements, such as rise and fall time, pulse width and propagation delay type measurements, without the need for additional circuitry or circuit duplication that would add to the overall cost of the time measurement architecture. Each of the critical building blocks are analysed and a description of the final implementation of a prototype chip using a 0.12m CMOS process is described.

As the on-chip clock speeds of high performance VLSI devices increase into the tens of gigahertz range, time measurement architectures with timing resolutions of tens of femtoseconds will be required. Current high resolution time measurements architectures based on vernier and flash time measurement architectures use latches and flip-flops in the main timing measurement technique and can suffer from the inherited metastability phenomenon. To address this problem, current research solutions are analysed in this thesis and an on-chip time measurement architecture that is also based on the time-to-digital conversion method but uses the homodyne technique is proposed. The architecture is described and finally simulations using transistors based on a 0.12m CMOS process are presented and suggest that timing resolutions in the tens of
femtosecond range are attainable.