Towards the neurocomputer: an investigation of VHDL neuron models

Abstract

The investigation of neuron structures is an incredibly difficult and complex task that yields relatively low rewards in terms of information from biological forms (either animals or tissue). The structures and connectivity of even the simplest invertebrates are almost impossible to establish with standard laboratory techniques, and even when this is possible it is generally time consuming, complex and expensive. Recent work has shown how a simplified behavioural approach to modelling neurons can allow “virtual” experiments to be carried out that map the behaviour of a simulated structure onto a hypothetical biological one, with correlation of behaviour rather than underlying connectivity. The problems with such approaches are numerous. The first is the difficulty of simulating realistic aggregates efficiently, the second is making sense of the results and finally, it would be helpful to have an implementation that could be synthesised to hardware for acceleration. This work presents a VHDL implementation of a neuron model which is verified through simulations of the Caenorhabditis Elegans (C.Elegans) locomotory system. The C.Elegans system is synthesized into hardware showing a massive improvement in simulation time because the hardware design runs in real-time, meaning a 19 second simulation takes 19 seconds vs. the 1.5 hours taken by the CAD simulation.

Logic cells using the VHDL neuron model are produced and verified through simulation to demonstrate the deterministic side of modelling neuronal circuits. The C.Elegans design is then analysed using these neuron logic cells to produce a simple logic version of C.Elegans which produces the same outputs given the same inputs as the Neuron C.Elegans model.

Finally the hardware neuron concept was extended to the case of a general purpose programmable neuron array designed to have 100 neurons and 200 synapses The configuration of the neurons and synapses is written to the device over a simple SPI bus, with a second SPI bus used to simultaneously write enable data and read the current states of the neuron outputs. The design was demonstrated to work correctly using the reference C.Elegans design.

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