Analysis of SiGe heterojunction integrated injection logic structures using a charge stored model

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Description/Abstract

A quasi two-dimensional stored charge model is developed as an aid to the optimisation of SiGe Integrated Injection Logic (I2L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I2L gate. Both the NpN switching transistor and the PNp load transistor are correctly modelled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I2L and the Ge and doping concentrations varied to determine the important trade-offs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NpN emitter layer. The inclusion of 16% Ge in the substrate-fed I2L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100ps should be achievable in SiGe I2L even at a geometry of 3mm. The model is applied to a realistic, self-aligned structure and a delay of 60 ps is predicted. It is expected that this performance can be improved with a fully optimised, scaled structure.