Synthesis of switched-current Ladder Derived Group delay Equalizers
Xie, Yan and Al Hashimi, Bashir (2002) Synthesis of switched-current Ladder Derived Group delay Equalizers. In, Proc. IEE Analog Signal Processing Symposium, Oxford, UK, , 1/1- 6/1.
Download
![[img]](http://eprints.soton.ac.uk/style/images/fileicons/application_pdf.png) |
PDF
Download (203Kb) |
Description/Abstract
This paper describes the design of switched-current group delay equalizers. The design process is based on the pole-zero mirroring technique; with equalizer z-transfer functions generated using an optimization algorithm. To facilitate the systematic implementation of the equalizers, a model describing the design process is developed. A novel feature of the equalizers implementation is that wave structures are employed in realizing the equalizer poles instead of integrators. MATLAB and SI simulation results based on a 6th-order equalizer are included. The results demonstrate that the equalizer can reduce the delay of a 5th-order, 1MHz lowpass SI elliptic filter from 155ns to <20ns over the entire filter bandwidth.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | Event Dates: 1 November 2002 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 258722 |
| Date Deposited: | 05 Jan 2004 |
| Last Modified: | 02 Mar 2012 03:05 |
| Contributors: | Xie, Yan (Author) Al Hashimi, Bashir (Author) |
| Date: | 2002 |
| Additional Information: | Event Dates: 1 November 2002 |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/258722 |
Actions (login required)
 |
View Item |
