Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
Spinks, SJ, Chalk, CD, Bell, IM and Zwolinski, M (2004) Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations. Journal of Electronic Testing: Theory and Applications, 20, (1), 11-23.
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Description/Abstract
The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.
| Item Type: | Article |
|---|---|
| ISSNs: | 0923-8174 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 258865 |
| Date Deposited: | 02 Mar 2005 |
| Last Modified: | 18 Aug 2012 03:24 |
| Contributors: | Spinks, SJ (Author) Chalk, CD (Author) Bell, IM (Author) Zwolinski, M (Author) |
| Date: | February 2004 |
| Status: | Published |
| Publisher: | Kluwer Academic Press |
| Further Information: | Google Scholar |
| ISI Citation Count: | 10 |
| URI: | http://eprints.soton.ac.uk/id/eprint/258865 |
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