Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance

Gili, E, Kunz, V D, de Groot, C H, Uchino, T, Ashburn, P, Donaghy, D C, Hall, S, Wang, Y and Hemment, P L F (2004) Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance. Solid State Electronics, (48), 511-519.


[img] PDF
Download (361Kb)


The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel legnth down to 100nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100mV. The short channel effects of the surround gate MOSFETs are investigated.

Item Type: Article
Keywords: Vertical MOSFETs, Parasitic capacitance, FILOX, Surround Gate, Double Gate
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
ePrint ID: 258908
Accepted Date and Publication Date:
Date Deposited: 27 Feb 2004
Last Modified: 31 Mar 2016 13:59
Further Information:Google Scholar

Actions (login required)

View Item View Item

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics