A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling

Uchino, Takashi, Ashburn, Peter, Kiyota, Yukihiro and Shiba, Takeo (2004) A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling. IEEE Transactions on Electron Devices, 51, (1), 14-19.


[img] PDF
Download (207Kb)


An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 omega/sq has been realised. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1um channel length and 40 percent higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25nm enables excellent dc and high-speed circuit performance in 0.1um devices

Item Type: Article
Keywords: CMOS Process, doping, junction, MOSFET
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
ePrint ID: 258916
Accepted Date and Publication Date:
January 2004Published
Date Deposited: 02 Mar 2005
Last Modified: 31 Mar 2016 13:59
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/258916

Actions (login required)

View Item View Item

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics