Reducing Power Dissipation in SRAM during Test

Abstract

In this paper we analyze the power consumption of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which permits to choose a specific addressing sequence. Further, the modified pre-charge logic allows also the switching between the normal functional mode and the low power test mode. We demonstrate that the modified pre-charge control circuitry has little or no effect on the memory performance. We analyze the sources of power consumption in functional and low power test mode, and we show how the power dissipation is computed for bit and word-oriented SRAMs. The efficiency of the proposed solution is validated through extensive Spice simulations for both bit-oriented and word-oriented SRAM.

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