Exploration of potential of strained-Si CMOS for ultra low-power circuit design


Ramakrishnan, Hiran, Chattopadhyay, Sanatan, Maharatna, Koushik, Shedable, S and Yakovlev, Alex (2007) Exploration of potential of strained-Si CMOS for ultra low-power circuit design. In, 8th International Conference on Ultimate Integration on Silicon, Lueven,

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Item Type: Conference or Workshop Item (Paper)
Keywords: Low power, strained silicon
Divisions: Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems
Item ID: 263530
Date Deposited: 19 Feb 2007
Last Modified: 02 Mar 2012 12:20
Contributors: Ramakrishnan, Hiran (Author)
Chattopadhyay, Sanatan (Author)
Maharatna, Koushik (Author)
Shedable, S (Author)
Yakovlev, Alex (Author)
Date: 2007
Status: Published
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/263530

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