Very Large Scale Integration Architecture for Integer Wavelet Transform

Abstract

The design of a new real-time integer-to-integer lifting-based wavelet transform (IWT) architecture is described. An efficient design method is proposed to construct an integrated programmable VLSI architecture that can operate as a forward or backward IWT in a pipelined fashion. The layout of the integrated VLSI structure is simple, modular, and cascadable for computing a wavelet transform based on 5/3 biorthogonal filters. The architecture is optimal with respect to both area and time and independent of the size of the input signal without requiring additional memory. The lifting steps are adapted to be causal and the proposed architecture is suitable for use in real-time processing applications. The critical path of the architecture is equal to the critical path of one lifting step. The numerical precision has been established using a Simulink model. Experimental tests have been made with 8-bit signed two's complement integer numbers. Based on the experimental results, the datapath width of the proposed architecture is fixed at 10 bits.

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Identifiers

ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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