Design of Fixed-Point Processing Based LDPC Codes Using EXIT Charts

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Description/Abstract

Logarithmic representation of the variables processed by iterative decoding algorithms of Low-Density Parity-Check (LDPC) codes are attractive, since the resultant reduced dynamic range of its Logarithmic Likelihood Ratios (LLRs) allows a Fixed Point (FP) operand-representation to be used. This FP representation has a lower computational complexity than a floating point representation, allowing the decoder's hardware to have a low energy consumption, which depends on the Operand-Width (OW) of the LLRs. However, if the OW is too low, then an inevitable performance degradation will be introduced. Therefore it is desirable to determine the minimum OW that does not impose a significant performance degradation. Previous efforts have advocated different OWs based on results obtained using time-consuming Bit Error Ratio (BER) simulations. However, these simulations are extremely time consuming, owing to the requirement of considering a range of channel Signal-to-Noise Ratios (SNRs). Therefore, in this paper, we propose the employment of EXtrinsic Information Transfer (EXIT) charts to overcome this drawback. Furthermore, EXIT charts analysis has the additional benefit of offering insights into the specific causes of the performance degradations encountered. Finally, a FP scheme having an overall OW = 6 is proposed for the implementation of the Min-Sum Algorithm (MSA).