Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation
Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (µeff), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that low-voltage testing improves detectability of bridge fault; this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.
Resistive bridge defects, transition delay test, process variation, logic test, low voltage test.
Zhong, Shida
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Khursheed, Saqib
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Al-Hashimi, Bashir
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Reddy, Sudhakar
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Chakrabarty, Krishnendu
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Zhong, Shida
8c250ea8-d473-4aed-b3c1-4fbcb17039b6
Khursheed, Saqib
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Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Reddy, Sudhakar
67e0e9b9-8788-489d-a0ed-7e42ab85594b
Chakrabarty, Krishnendu
a8afcb71-145f-4def-ac52-e03ecc47863f
Zhong, Shida, Khursheed, Saqib, Al-Hashimi, Bashir, Reddy, Sudhakar and Chakrabarty, Krishnendu
(2011)
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Asian Test Symposium 2011, New Delhi, India.
21 - 23 Nov 2011.
(In Press)
Record type:
Conference or Workshop Item
(Other)
Abstract
Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (µeff), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that low-voltage testing improves detectability of bridge fault; this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.
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ats2011_129.pdf
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More information
Accepted/In Press date: 17 August 2011
Additional Information:
Event Dates: 21-23 November, 2011
Venue - Dates:
Asian Test Symposium 2011, New Delhi, India, 2011-11-21 - 2011-11-23
Keywords:
Resistive bridge defects, transition delay test, process variation, logic test, low voltage test.
Organisations:
Electronic & Software Systems, EEE
Identifiers
Local EPrints ID: 272678
URI: http://eprints.soton.ac.uk/id/eprint/272678
PURE UUID: cbf3ceea-8289-40b1-9fe9-90f87a7d0c44
Catalogue record
Date deposited: 17 Aug 2011 16:24
Last modified: 14 Mar 2024 10:07
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Contributors
Author:
Shida Zhong
Author:
Saqib Khursheed
Author:
Bashir Al-Hashimi
Author:
Sudhakar Reddy
Author:
Krishnendu Chakrabarty
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