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Can clock faults be detected through functional test?

Can clock faults be detected through functional test?
Can clock faults be detected through functional test?
We analyze the probability to detect clock faults indirectly through conventional functional testing by considering realistic datapaths derived from ISCAS'85 benchmarks. We show that, even optimistically assuming that we are able to test all short and long paths for min and max delay violations, the detection of clock faults can not be guaranteed, thus mandating new, specific testing approaches for clock faults, otherwise possibly compromising the system correct operation in the field, with dramatic consequences on product quality and defect level.
1-4244-0185-2
168-171
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Cazeaux, Jose' Manuel
de02151c-4f59-4686-a730-18f78d372562
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Cazeaux, Jose' Manuel
de02151c-4f59-4686-a730-18f78d372562

Metra, Cecilia, Rossi, Daniele, Omana, Martin and Cazeaux, Jose' Manuel (2006) Can clock faults be detected through functional test? 2006 IEEE Design & Diagnostics in Electronic Circuits and Systems, Prague, Czech Republic. 18 - 21 Apr 2006. pp. 168-171 . (doi:10.1109/DDECS.2006.1649606).

Record type: Conference or Workshop Item (Paper)

Abstract

We analyze the probability to detect clock faults indirectly through conventional functional testing by considering realistic datapaths derived from ISCAS'85 benchmarks. We show that, even optimistically assuming that we are able to test all short and long paths for min and max delay violations, the detection of clock faults can not be guaranteed, thus mandating new, specific testing approaches for clock faults, otherwise possibly compromising the system correct operation in the field, with dramatic consequences on product quality and defect level.

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More information

Published date: April 2006
Venue - Dates: 2006 IEEE Design & Diagnostics in Electronic Circuits and Systems, Prague, Czech Republic, 2006-04-18 - 2006-04-21
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 368899
URI: http://eprints.soton.ac.uk/id/eprint/368899
ISBN: 1-4244-0185-2
PURE UUID: f789643e-2301-4f1b-817e-94138cbd54ed

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Date deposited: 06 Oct 2014 13:18
Last modified: 14 Mar 2024 17:55

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Contributors

Author: Cecilia Metra
Author: Daniele Rossi
Author: Martin Omana
Author: Jose' Manuel Cazeaux

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