Energy-efficient hardware implementation of LR-aided K-Best MIMO decoder for 5G networks
Energy-efficient hardware implementation of LR-aided K-Best MIMO decoder for 5G networks
Energy efficiency is a primary design goal for future green wireless communication technologies. Multiple-input multiple-output (MIMO) schemes have been proposed in literature to improve the throughput of communication systems, they are expected to play a prominent role in the upcoming 5th generation (5G) standard. This paper presents a novel high efficiency MIMO decoder based on the K-Best algorithm with lattice reduction. We have designed a novel hardware architecture for this decoder, which was implemented using 32nm standard CMOS technology. Our results show that the proposed decoder can achieve on average a four-fold reduction in the power costs compared to recently published designs for 5G networks. The throughput of the design is 506 Mbits/sec, which is comparable to existing designs.
sphere decoding (SD), lattice reduction, k-best algorithm, MIMO, green communication, low power, VLSI, hardware design
1-10
Halak, Basel
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El-Hajjar, Mohammed
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Toma, Ogeen H.
fb9f5e82-cb9c-413e-942a-628497821b8c
Cheng, Zhuofan
19364c41-0912-4624-a4c2-f70aea853bcf
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
El-Hajjar, Mohammed
3a829028-a427-4123-b885-2bab81a44b6f
Toma, Ogeen H.
fb9f5e82-cb9c-413e-942a-628497821b8c
Cheng, Zhuofan
19364c41-0912-4624-a4c2-f70aea853bcf
Halak, Basel, El-Hajjar, Mohammed, Toma, Ogeen H. and Cheng, Zhuofan
(2016)
Energy-efficient hardware implementation of LR-aided K-Best MIMO decoder for 5G networks.
Journal of Low Power Electronics and Applications, 6 (12), .
(doi:10.3390/jlpea6030012).
Abstract
Energy efficiency is a primary design goal for future green wireless communication technologies. Multiple-input multiple-output (MIMO) schemes have been proposed in literature to improve the throughput of communication systems, they are expected to play a prominent role in the upcoming 5th generation (5G) standard. This paper presents a novel high efficiency MIMO decoder based on the K-Best algorithm with lattice reduction. We have designed a novel hardware architecture for this decoder, which was implemented using 32nm standard CMOS technology. Our results show that the proposed decoder can achieve on average a four-fold reduction in the power costs compared to recently published designs for 5G networks. The throughput of the design is 506 Mbits/sec, which is comparable to existing designs.
Text
jlpea-06-00012.pdf
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More information
Accepted/In Press date: 11 July 2016
e-pub ahead of print date: 14 July 2016
Keywords:
sphere decoding (SD), lattice reduction, k-best algorithm, MIMO, green communication, low power, VLSI, hardware design
Organisations:
EEE
Identifiers
Local EPrints ID: 398635
URI: http://eprints.soton.ac.uk/id/eprint/398635
ISSN: 2079-9268
PURE UUID: 4b7b080d-9e98-4388-ab65-90d2ed94e088
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Date deposited: 28 Jul 2016 10:13
Last modified: 15 Mar 2024 03:42
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Contributors
Author:
Basel Halak
Author:
Mohammed El-Hajjar
Author:
Ogeen H. Toma
Author:
Zhuofan Cheng
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