Loss comparison of 2 and 3-level inverter topologies
Orfanoudakis, G., Sharkh, S., Abu-Sara, M. and Yuratich, M. (2010) Loss comparison of 2 and 3-level inverter topologies. In, 5th IET International Conference on Power Electronics, Machines and Drives (PEMD), Brighton, UK, 19 - 21 Apr 2010. 6pp.
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Official URL: http://conferences.theiet.org/pemd/index2.htm
Description/Abstract
This paper investigates semiconductor and DC-link capacitor losses in two two-level and two three-level voltage source inverters. The components of the four inverters are selected to have appropriate voltage and current ratings. Analytical expressions for semiconductor losses are reviewed and expressions for DC link capacitor losses are derived for all topologies. Three-level inverters are found to have lower semiconductor losses, but higher DC-link capacitor losses. Overall, the three-level Neutral-Point-Clamped inverter proved to be the most efficient topology.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Related URLs: | http://conferences.theiet.org/...index2.htm |
| Subjects: | T Technology > T Technology (General) |
| Divisions: | University Structure - Pre August 2011 > School of Engineering Sciences > Electro-Mechanical Engineering |
| ePrint ID: | 73529 |
| Deposited On: | 16 Mar 2010 |
| Last Modified: | 22 Dec 2010 01:10 |
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