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Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B

Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B
Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B
Modern System-on-chip (SoC) hardware design puts considerable pressure on existing design and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for efficient architectural exploration and re-use. The existing methods for taking a high-level paper specification and refining this specification to an implementation that meets its performance criteria is largely manual and error-prone and as RTL descriptions get larger, a systematic design method is necessary to address explicitly the timing issues that arise when applying logic synthesis to such large blocks.

Guarded Atomic Actions have been shown to offer a convenient notation for describing microarchitectures that is amenable to formal reasoning and high-level synthesis. Event-B is a language and method that supports the development of specifications with automatic proof and refinement, based on guarded atomic actions. Latency-insensitive design ensures that a design composed of functionally correct components will be independent of communication latency. A method has been developed which uses Event-B for latency-insensitive SoC component and sub-system design which can be combined with high-level, component synthesis to enable architectural exploration and re-use at the specification level and to close the specification gap in the SoC hardware flow.
Colley, John
d2877837-a2f2-4f84-b3f3-3ffe79ffeb87
Colley, John
d2877837-a2f2-4f84-b3f3-3ffe79ffeb87
Butler, Michael
54b9c2c7-2574-438e-9a36-6842a3d53ed0

Colley, John (2010) Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B. University of Southampton, School of Electronics and Computer Science, Doctoral Thesis, 187pp.

Record type: Thesis (Doctoral)

Abstract

Modern System-on-chip (SoC) hardware design puts considerable pressure on existing design and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for efficient architectural exploration and re-use. The existing methods for taking a high-level paper specification and refining this specification to an implementation that meets its performance criteria is largely manual and error-prone and as RTL descriptions get larger, a systematic design method is necessary to address explicitly the timing issues that arise when applying logic synthesis to such large blocks.

Guarded Atomic Actions have been shown to offer a convenient notation for describing microarchitectures that is amenable to formal reasoning and high-level synthesis. Event-B is a language and method that supports the development of specifications with automatic proof and refinement, based on guarded atomic actions. Latency-insensitive design ensures that a design composed of functionally correct components will be independent of communication latency. A method has been developed which uses Event-B for latency-insensitive SoC component and sub-system design which can be combined with high-level, component synthesis to enable architectural exploration and re-use at the specification level and to close the specification gap in the SoC hardware flow.

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Published date: November 2010
Organisations: University of Southampton

Identifiers

Local EPrints ID: 171695
URI: http://eprints.soton.ac.uk/id/eprint/171695
PURE UUID: e18d5673-1bb9-4017-93d8-e8d536bbf236
ORCID for Michael Butler: ORCID iD orcid.org/0000-0003-4642-5373

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Date deposited: 18 Jan 2011 16:23
Last modified: 30 Jan 2020 01:27

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Contributors

Author: John Colley
Thesis advisor: Michael Butler ORCID iD

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