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Mimimising Power Dissipation During Test Application in Full Scan Sequential Circuits by Primary Input Freezing

Mimimising Power Dissipation During Test Application in Full Scan Sequential Circuits by Primary Input Freezing
Mimimising Power Dissipation During Test Application in Full Scan Sequential Circuits by Primary Input Freezing
This paper describes a new technique for minimising power dissipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. This paper presents a new algorithm which determines the primary input change time such that maximum saving in transition count is achieved with respect to a given test vector and scan latch order. It is shown how combining the proposed technique with the recently reported scan latch and test vector ordering yields further reductions in power dissipation during test application. Exhaustive experimental results using compact and non compact test sets demonstrate substantial savings in power dissipation using a simulated annealing-based design space exploration. As an example saving of 34% in power dissipation for benchmark circuit s713 is achieved.
313-322
Nicolici, N.
9be70b5e-becc-4ec4-a564-14758ef4f03c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Williams, A.C.
24f37520-cb05-45ba-80da-cc4d0211722d
Nicolici, N.
9be70b5e-becc-4ec4-a564-14758ef4f03c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Williams, A.C.
24f37520-cb05-45ba-80da-cc4d0211722d

Nicolici, N., Al-Hashimi, B.M. and Williams, A.C. (2000) Mimimising Power Dissipation During Test Application in Full Scan Sequential Circuits by Primary Input Freezing IEE Proceedings - Computers and Digital Techniques, 147, (5), pp. 313-322.

Record type: Article

Abstract

This paper describes a new technique for minimising power dissipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. This paper presents a new algorithm which determines the primary input change time such that maximum saving in transition count is achieved with respect to a given test vector and scan latch order. It is shown how combining the proposed technique with the recently reported scan latch and test vector ordering yields further reductions in power dissipation during test application. Exhaustive experimental results using compact and non compact test sets demonstrate substantial savings in power dissipation using a simulated annealing-based design space exploration. As an example saving of 34% in power dissipation for benchmark circuit s713 is achieved.

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Published date: September 2000
Additional Information: Organisation: IEE
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 252021
URI: http://eprints.soton.ac.uk/id/eprint/252021
PURE UUID: 57c363ed-16b1-482b-ba97-e73d8a857f0f

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Date deposited: 18 Oct 2000
Last modified: 24 Jul 2017 16:42

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Contributors

Author: N. Nicolici
Author: B.M. Al-Hashimi
Author: A.C. Williams

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