A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket
A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket
A novel architecture for a vertical MOSFET is proposed and initial investigations conducted by numerical simulation.
347-350
Lamb, A. C.
89571b4c-7c59-47e8-9325-e85e0d70a407
Riley, L. S.
c7094e82-8559-4b23-9a88-93552e080e0b
Hall, S.
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Kunz, V.D.
c4efd0d1-d850-414d-9c33-12029ac3e060
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
September 2001
Lamb, A. C.
89571b4c-7c59-47e8-9325-e85e0d70a407
Riley, L. S.
c7094e82-8559-4b23-9a88-93552e080e0b
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Kunz, V.D.
c4efd0d1-d850-414d-9c33-12029ac3e060
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Lamb, A. C., Riley, L. S., Hall, S., Kunz, V.D., de Groot, C.H. and Ashburn, P.
(2001)
A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket.
ESSDERC 2001.
.
Record type:
Conference or Workshop Item
(Other)
Abstract
A novel architecture for a vertical MOSFET is proposed and initial investigations conducted by numerical simulation.
More information
Published date: September 2001
Additional Information:
Address: Not Known
Venue - Dates:
ESSDERC 2001, 2001-09-01
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 256162
URI: http://eprints.soton.ac.uk/id/eprint/256162
PURE UUID: b86818e6-a582-435d-8318-5e62d4a3894f
Catalogue record
Date deposited: 07 Jul 2003
Last modified: 15 Mar 2024 03:11
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Contributors
Author:
A. C. Lamb
Author:
L. S. Riley
Author:
S. Hall
Author:
V.D. Kunz
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