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A lock-step synchronization algorithm for logic simulation in a multi-solver environment

Kazmierski, T. J., Wang, X. and Mrcarica, Z. (1994) A lock-step synchronization algorithm for logic simulation in a multi-solver environment At Proc. ASIC'94 Conf., Bejing.

Record type: Conference or Workshop Item (Other)
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Published date: October 1994
Venue - Dates: Proc. ASIC'94 Conf., Bejing, 1994-10-01
Organisations: EEE

Identifiers

Local EPrints ID: 256525
URI: http://eprints.soton.ac.uk/id/eprint/256525
PURE UUID: f63647cd-41e2-40e9-a31c-10dc448bb7d3

Catalogue record

Date deposited: 25 Apr 2002
Last modified: 18 Jul 2017 09:45

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Contributors

Author: T. J. Kazmierski
Author: X. Wang
Author: Z. Mrcarica

University divisions

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