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The Design of a Hierarchical Circuit-Level Simulator

The Design of a Hierarchical Circuit-Level Simulator
The Design of a Hierarchical Circuit-Level Simulator
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Nichols, KG
468ecfdb-e249-4266-80c6-84a4d235aa6f
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Nichols, KG
468ecfdb-e249-4266-80c6-84a4d235aa6f

(1984) The Design of a Hierarchical Circuit-Level Simulator Zwolinski, M and Nichols, KG (eds.) At Electronic Design Automation.

Record type: Conference or Workshop Item (Other)
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More information

Published date: 1984
Additional Information: Event Dates: March 1984
Venue - Dates: Electronic Design Automation, 1984-03-01
Organisations: EEE

Identifiers

Local EPrints ID: 257684
URI: http://eprints.soton.ac.uk/id/eprint/257684
PURE UUID: 5dcf5b5e-8cb0-44b3-843e-c862b4fb1b2e
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 17 Jun 2003
Last modified: 18 Jul 2017 09:36

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Contributors

Editor: M Zwolinski ORCID iD
Editor: KG Nichols

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