The University of Southampton
University of Southampton Institutional Repository

Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation

Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation
Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their oayout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned procfess has been developed to reduce the parasitic overlap capacitance in MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM)which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.
LOCOS oxidation, parasitic capacitance, surround-gate, vertical MOSFETs
1487-1493
Kunz, V Dominik
6f1151e3-be12-436f-8a65-7a47ca8640c9
Uchino, Takashi
53356d82-f008-4b0e-8c7e-359c0d283b6c
de Groot, C.H.(Kees)
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Donaghy, David C
763c2bf3-70dd-468d-b1a5-aecc6f61832f
Hall, Steven
b11370a5-759c-478b-8ba2-ad04140dc4fd
Wang, Yun
d0ddd51d-60a2-4c8a-b65e-6b5068a0e0c1
Hemment, Peter L F
d9ad8e6f-0343-487b-8821-2d6e1f98833d
Kunz, V Dominik
6f1151e3-be12-436f-8a65-7a47ca8640c9
Uchino, Takashi
53356d82-f008-4b0e-8c7e-359c0d283b6c
de Groot, C.H.(Kees)
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Donaghy, David C
763c2bf3-70dd-468d-b1a5-aecc6f61832f
Hall, Steven
b11370a5-759c-478b-8ba2-ad04140dc4fd
Wang, Yun
d0ddd51d-60a2-4c8a-b65e-6b5068a0e0c1
Hemment, Peter L F
d9ad8e6f-0343-487b-8821-2d6e1f98833d

Kunz, V Dominik, Uchino, Takashi, de Groot, C.H.(Kees), Ashburn, Peter, Donaghy, David C, Hall, Steven, Wang, Yun and Hemment, Peter L F (2003) Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation. IEEE Transactions on Electron Devices, 50 (6), 1487-1493.

Record type: Article

Abstract

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their oayout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned procfess has been developed to reduce the parasitic overlap capacitance in MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM)which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Text
2003_filox_paper.pdf - Other
Download (809kB)

More information

Published date: June 2003
Keywords: LOCOS oxidation, parasitic capacitance, surround-gate, vertical MOSFETs
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 258035
URI: http://eprints.soton.ac.uk/id/eprint/258035
PURE UUID: 6af4d26b-0a9d-4b2b-9cf7-b9e2e00f21c9
ORCID for C.H.(Kees) de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 22 Dec 2003
Last modified: 01 Oct 2019 00:53

Export record

Contributors

Author: V Dominik Kunz
Author: Takashi Uchino
Author: Peter Ashburn
Author: David C Donaghy
Author: Steven Hall
Author: Yun Wang
Author: Peter L F Hemment

University divisions

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×