Electrical Characteristics of Single, Double and Surround Gate Vertical MOSFETs with Reduced Overlap Capacitance
Electrical Characteristics of Single, Double and Surround Gate Vertical MOSFETs with Reduced Overlap Capacitance
The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50nm. Surround gate structures can be realised which offer improved short channel effects and more channel with per unit silicon area. In this paper, a low technology overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated
0-7803-7999-3/03
171-174
Gili, E
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Kunz, V D
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de Groot, C H
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Uchino, T
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Donaghy, D
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Hall, S
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Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
2003
Gili, E
68792585-bbb1-4358-a8ca-c1b4b012cb4e
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Uchino, T
5c7413a3-c3f6-41ee-8a74-1614054f63e4
Donaghy, D
b6269fe1-629c-4d66-afcb-ad9752db6a49
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Gili, E, Kunz, V D, de Groot, C H, Uchino, T, Donaghy, D, Hall, S and Ashburn, P
(2003)
Electrical Characteristics of Single, Double and Surround Gate Vertical MOSFETs with Reduced Overlap Capacitance.
33rd European Solid State Device Research Conference, Estoril, Portugal.
16 - 18 Sep 2003.
.
Record type:
Conference or Workshop Item
(Poster)
Abstract
The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50nm. Surround gate structures can be realised which offer improved short channel effects and more channel with per unit silicon area. In this paper, a low technology overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated
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ESSDERC_2003.pdf
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Published date: 2003
Additional Information:
Event Dates: 16-18th September 2003
Venue - Dates:
33rd European Solid State Device Research Conference, Estoril, Portugal, 2003-09-16 - 2003-09-18
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 258288
URI: http://eprints.soton.ac.uk/id/eprint/258288
ISBN: 0-7803-7999-3/03
PURE UUID: 2d21afe2-ae06-43bf-b584-c434b8bf0802
Catalogue record
Date deposited: 30 Nov 2004
Last modified: 15 Mar 2024 03:11
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Contributors
Author:
E Gili
Author:
V D Kunz
Author:
T Uchino
Author:
D Donaghy
Author:
S Hall
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