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Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

Spinks, SJ, Chalk, CD, Bell, IM and Zwolinski, M (2004) Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations Journal of Electronic Testing, Theory and Applications (JETTA), 20, (1), pp. 11-23.

Record type: Article


The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.

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Published date: February 2004
Organisations: EEE


Local EPrints ID: 258865
ISSN: 0923-8174
PURE UUID: 517265db-36bd-493b-b731-7501c2d22d5d
ORCID for M Zwolinski: ORCID iD

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Date deposited: 02 Mar 2005
Last modified: 18 Jul 2017 09:29

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Author: SJ Spinks
Author: CD Chalk
Author: IM Bell
Author: M Zwolinski ORCID iD

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