Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance
Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance
The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel length down to 100nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100mV. The short channel effects of the surround gate MOSFETs are investigated.
Vertical MOSFETs, Parasitic capacitance, FILOX, Surround Gate, Double Gate
511-519
Gili, E
68792585-bbb1-4358-a8ca-c1b4b012cb4e
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Uchino, T
5c7413a3-c3f6-41ee-8a74-1614054f63e4
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Donaghy, D C
e7984c55-b15d-4a82-868c-da3eb63f50c2
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
Wang, Y
adc6c787-e577-46bf-bda7-740d56e7d554
Hemment, P L F
94618b9c-dba6-4cf6-b4d9-8770e7081532
2004
Gili, E
68792585-bbb1-4358-a8ca-c1b4b012cb4e
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Uchino, T
5c7413a3-c3f6-41ee-8a74-1614054f63e4
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Donaghy, D C
e7984c55-b15d-4a82-868c-da3eb63f50c2
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
Wang, Y
adc6c787-e577-46bf-bda7-740d56e7d554
Hemment, P L F
94618b9c-dba6-4cf6-b4d9-8770e7081532
Gili, E, Kunz, V D, de Groot, C H, Uchino, T, Ashburn, P, Donaghy, D C, Hall, S, Wang, Y and Hemment, P L F
(2004)
Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance.
Solid-State Electronics, (48), .
Abstract
The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel length down to 100nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100mV. The short channel effects of the surround gate MOSFETs are investigated.
More information
Published date: 2004
Keywords:
Vertical MOSFETs, Parasitic capacitance, FILOX, Surround Gate, Double Gate
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 258908
URI: http://eprints.soton.ac.uk/id/eprint/258908
ISSN: 0038-1101
PURE UUID: 3676b4dd-a900-433c-b212-9c050a6278ad
Catalogue record
Date deposited: 27 Feb 2004
Last modified: 15 Mar 2024 03:11
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Contributors
Author:
E Gili
Author:
V D Kunz
Author:
T Uchino
Author:
D C Donaghy
Author:
S Hall
Author:
Y Wang
Author:
P L F Hemment
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