Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance


Gili, E, Kunz, V D, de Groot, C H, Uchino, T, Ashburn, P, Donaghy, D C, Hall, S, Wang, Y and Hemment, P L F (2004) Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance Solid State Electronics, (48), pp. 511-519.

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Description/Abstract

The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel legnth down to 100nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100mV. The short channel effects of the surround gate MOSFETs are investigated.

Item Type: Article
ISSNs: 0038-1101 (print)
Keywords: Vertical MOSFETs, Parasitic capacitance, FILOX, Surround Gate, Double Gate
Organisations: Nanoelectronics and Nanotechnology
ePrint ID: 258908
Date :
Date Event
2004Published
Date Deposited: 27 Feb 2004
Last Modified: 17 Apr 2017 22:39
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/258908

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