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Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance

Gili, E, Kunz, V D, de Groot, C H, Uchino, T, Ashburn, P, Donaghy, D C, Hall, S, Wang, Y and Hemment, P L F (2004) Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance Solid State Electronics, (48), pp. 511-519.

Record type: Article

Abstract

The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel legnth down to 100nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100mV. The short channel effects of the surround gate MOSFETs are investigated.

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Published date: 2004
Keywords: Vertical MOSFETs, Parasitic capacitance, FILOX, Surround Gate, Double Gate
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 258908
URI: http://eprints.soton.ac.uk/id/eprint/258908
ISSN: 0038-1101
PURE UUID: 3676b4dd-a900-433c-b212-9c050a6278ad
ORCID for C H de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 27 Feb 2004
Last modified: 18 Jul 2017 09:29

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Contributors

Author: E Gili
Author: V D Kunz
Author: C H de Groot ORCID iD
Author: T Uchino
Author: P Ashburn
Author: D C Donaghy
Author: S Hall
Author: Y Wang
Author: P L F Hemment

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