A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling
A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling
An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 Ω/sq has been realised. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1µm channel length and 40 percent higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25nm enables excellent dc and high-speed circuit performance in 0.1µm devices
CMOS Process, doping, junction, MOSFET
14-19
Uchino, Takashi
53356d82-f008-4b0e-8c7e-359c0d283b6c
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Kiyota, Yukihiro
54416328-52c0-4923-b8ea-c4b223c652ad
Shiba, Takeo
0d61d267-ece4-48d5-aad8-84ba9ecc85f1
January 2004
Uchino, Takashi
53356d82-f008-4b0e-8c7e-359c0d283b6c
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Kiyota, Yukihiro
54416328-52c0-4923-b8ea-c4b223c652ad
Shiba, Takeo
0d61d267-ece4-48d5-aad8-84ba9ecc85f1
Uchino, Takashi, Ashburn, Peter, Kiyota, Yukihiro and Shiba, Takeo
(2004)
A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling.
IEEE Transactions on Electron Devices, 51 (1), .
Abstract
An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 Ω/sq has been realised. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1µm channel length and 40 percent higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25nm enables excellent dc and high-speed circuit performance in 0.1µm devices
Text
2003_Uchino_RVD_process.pdf
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More information
Published date: January 2004
Keywords:
CMOS Process, doping, junction, MOSFET
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 258916
URI: http://eprints.soton.ac.uk/id/eprint/258916
PURE UUID: c41ca04b-6b60-44af-88bf-6d693481fa2d
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Date deposited: 02 Mar 2005
Last modified: 14 Mar 2024 06:15
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Contributors
Author:
Takashi Uchino
Author:
Yukihiro Kiyota
Author:
Takeo Shiba
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