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A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling

Uchino, Takashi, Ashburn, Peter, Kiyota, Yukihiro and Shiba, Takeo (2004) A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling IEEE Transactions on Electron Devices, 51, (1), pp. 14-19.

Record type: Article


An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 omega/sq has been realised. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1um channel length and 40 percent higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25nm enables excellent dc and high-speed circuit performance in 0.1um devices

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Published date: January 2004
Keywords: CMOS Process, doping, junction, MOSFET
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 258916
PURE UUID: c41ca04b-6b60-44af-88bf-6d693481fa2d

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Date deposited: 02 Mar 2005
Last modified: 18 Jul 2017 09:29

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Author: Takashi Uchino
Author: Peter Ashburn
Author: Yukihiro Kiyota
Author: Takeo Shiba

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