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Design of 50nm Vertical MOSFET Incorporating a Dielectric Pocket

Design of 50nm Vertical MOSFET Incorporating a Dielectric Pocket
Design of 50nm Vertical MOSFET Incorporating a Dielectric Pocket
A new architecture for a vertical MOS transistor is proposed that incorporates a so-calle dielectric pocket (DP) for suppression of short channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel legnth with more relaxed lithography.
Dielectric pocket, short-channel effects, SCEs, Si devices vertical MOSFET
158-161
Donaghy, D
b6269fe1-629c-4d66-afcb-ad9752db6a49
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Donaghy, D
b6269fe1-629c-4d66-afcb-ad9752db6a49
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Donaghy, D, Hall, S, de Groot, C H, Kunz, V D and Ashburn, P (2004) Design of 50nm Vertical MOSFET Incorporating a Dielectric Pocket. IEEE Transactions on Electron Devices, 51 (1), 158-161.

Record type: Article

Abstract

A new architecture for a vertical MOS transistor is proposed that incorporates a so-calle dielectric pocket (DP) for suppression of short channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel legnth with more relaxed lithography.

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More information

Published date: January 2004
Keywords: Dielectric pocket, short-channel effects, SCEs, Si devices vertical MOSFET
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 258918
URI: https://eprints.soton.ac.uk/id/eprint/258918
PURE UUID: 087d8f09-5400-4aa7-8e10-bbc508a55281
ORCID for C H de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 27 Feb 2004
Last modified: 19 Jul 2019 01:01

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