Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process

Abstract

Enhanced performance is demonstrated from a buried, compressively strained-Si0.7Ge0.3 p-MOSFET fabricated on a relaxed Si0.85Ge0.15 using a high thermal budget 0.25 µm CMOS process. The devices are designed to be fully compatible with a strained-Si CMOS process but offers a number of potential benefits over a surface channel p-MOSFET for certain circuit applications. Transconductance, on-current, hole velocity and mobility enhancements are observed over surface strained-Si channel devices on both Si0.85Ge0.15 and Si0.8Ge0.2 virtual substrates and the bulk Si control devices for constant effective channel length. The buried channel devices exhibit enhancements over the Si control devices of 93% in on-current and 62% in hole velocity for 0.25 µm effective channel length devices without compromising the subthreshold characteristics. The extracted effective mobility for the buried channel device is over 40% greater than the universal mobility curve for bulk Si p-MOS devices at 0.55 MV/cm vertical effective electric fields. Index Terms—CMOS, p-MOSFET, strained-Si, SiGe, quantum well, thermal budget, drain current enhancements, transconductance enhancements, virtual substrate.

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