The University of Southampton
University of Southampton Institutional Repository

Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process

Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process
Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process
Enhanced performance is demonstrated from a buried, compressively strained-Si0.7Ge0.3 p-MOSFET fabricated on a relaxed Si0.85Ge0.15 using a high thermal budget 0.25 µm CMOS process. The devices are designed to be fully compatible with a strained-Si CMOS process but offers a number of potential benefits over a surface channel p-MOSFET for certain circuit applications. Transconductance, on-current, hole velocity and mobility enhancements are observed over surface strained-Si channel devices on both Si0.85Ge0.15 and Si0.8Ge0.2 virtual substrates and the bulk Si control devices for constant effective channel length. The buried channel devices exhibit enhancements over the Si control devices of 93% in on-current and 62% in hole velocity for 0.25 µm effective channel length devices without compromising the subthreshold characteristics. The extracted effective mobility for the buried channel device is over 40% greater than the universal mobility curve for bulk Si p-MOS devices at 0.55 MV/cm vertical effective electric fields. Index Terms—CMOS, p-MOSFET, strained-Si, SiGe, quantum well, thermal budget, drain current enhancements, transconductance enhancements, virtual substrate.
Temple, Matthew P.
942d4f51-ca6a-4e78-96c4-bd4f142f7e10
Paul, Douglas J.
fb94dd5c-911b-4c0b-bbe4-42a58f0ce03d
Tang, Yue T.
e944297b-6a69-4f74-9d6d-59f0751b3975
Waite, Andrew M.
3badd40f-fa77-443f-8c8c-baede8a20dbd
Cerrina, Claudia
80f30b6e-cc82-427a-a84b-817f660d112f
Evans, Alan G.R.
082f720d-3830-46d7-ba87-b058af733bc3
Li, Xiabbing
5e4a046d-1fb8-4dbd-a7e3-9e0fd520aa84
Zhang, Jing
d6afba24-5cbe-4ff1-967f-486e75419b99
Olsen, Sarah H.
c6d5e012-c9f3-4f1b-af45-b624a863e152
O’Neill, Anthony G.
1cc2ebda-125f-4741-81bc-1956e6a71555
Temple, Matthew P.
942d4f51-ca6a-4e78-96c4-bd4f142f7e10
Paul, Douglas J.
fb94dd5c-911b-4c0b-bbe4-42a58f0ce03d
Tang, Yue T.
e944297b-6a69-4f74-9d6d-59f0751b3975
Waite, Andrew M.
3badd40f-fa77-443f-8c8c-baede8a20dbd
Cerrina, Claudia
80f30b6e-cc82-427a-a84b-817f660d112f
Evans, Alan G.R.
082f720d-3830-46d7-ba87-b058af733bc3
Li, Xiabbing
5e4a046d-1fb8-4dbd-a7e3-9e0fd520aa84
Zhang, Jing
d6afba24-5cbe-4ff1-967f-486e75419b99
Olsen, Sarah H.
c6d5e012-c9f3-4f1b-af45-b624a863e152
O’Neill, Anthony G.
1cc2ebda-125f-4741-81bc-1956e6a71555

Temple, Matthew P., Paul, Douglas J., Tang, Yue T., Waite, Andrew M., Cerrina, Claudia, Evans, Alan G.R., Li, Xiabbing, Zhang, Jing, Olsen, Sarah H. and O’Neill, Anthony G. (2004) Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process. IEEE Transactions Electronic Devices.

Record type: Article

Abstract

Enhanced performance is demonstrated from a buried, compressively strained-Si0.7Ge0.3 p-MOSFET fabricated on a relaxed Si0.85Ge0.15 using a high thermal budget 0.25 µm CMOS process. The devices are designed to be fully compatible with a strained-Si CMOS process but offers a number of potential benefits over a surface channel p-MOSFET for certain circuit applications. Transconductance, on-current, hole velocity and mobility enhancements are observed over surface strained-Si channel devices on both Si0.85Ge0.15 and Si0.8Ge0.2 virtual substrates and the bulk Si control devices for constant effective channel length. The buried channel devices exhibit enhancements over the Si control devices of 93% in on-current and 62% in hole velocity for 0.25 µm effective channel length devices without compromising the subthreshold characteristics. The extracted effective mobility for the buried channel device is over 40% greater than the universal mobility curve for bulk Si p-MOS devices at 0.55 MV/cm vertical effective electric fields. Index Terms—CMOS, p-MOSFET, strained-Si, SiGe, quantum well, thermal budget, drain current enhancements, transconductance enhancements, virtual substrate.

Text
buried3.pdf - Other
Download (631kB)

More information

Published date: March 2004
Additional Information: Y. T. Tang, A. M. Waite, C. Cerrina and A.G. R. Evans were with the Department of Electronics and Computer Science, University of Southampton.
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 258971
URI: http://eprints.soton.ac.uk/id/eprint/258971
PURE UUID: 2e360f92-b38c-40af-aac4-b11f33e9ae9a

Catalogue record

Date deposited: 10 Sep 2004
Last modified: 14 Mar 2024 06:16

Export record

Contributors

Author: Matthew P. Temple
Author: Douglas J. Paul
Author: Yue T. Tang
Author: Andrew M. Waite
Author: Claudia Cerrina
Author: Alan G.R. Evans
Author: Xiabbing Li
Author: Jing Zhang
Author: Sarah H. Olsen
Author: Anthony G. O’Neill

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×