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High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture

High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture
High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture
Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si0.7Ge0.3 on an Si0.85Ge0.15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.
CMOS, drain-current enhancement, nMOSFETs, self-heating, SiGe, strained silicon, thermal budget, transconductance enhancement, virtual substrate
1961-1969
Olsen, S.H.
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O’Neill, A.G.
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Driscoll, L.S.
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Kwa, K.S.K
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Chattopadhyay, S.
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Waite, A.M.
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Tang, Y.T.
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Evans, A.G.R.
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Norris, D.J.
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Cullis, A.G.
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Paul, D.J.
d16dbdf8-e83a-4629-810b-dd877ce34e34
Robbins, D.J.
a7e1052f-8f34-41dd-b822-ad2bce3fe91b
Olsen, S.H.
c6d5e012-c9f3-4f1b-af45-b624a863e152
O’Neill, A.G.
1cc2ebda-125f-4741-81bc-1956e6a71555
Driscoll, L.S.
d780b102-86d0-40ae-b8e6-a0eaf8f6879c
Kwa, K.S.K
64f2c272-15a7-47a2-807b-a87bbe320154
Chattopadhyay, S.
4a7c7b4f-f3fb-41ee-8eb2-9eb9bf6706ee
Waite, A.M.
3badd40f-fa77-443f-8c8c-baede8a20dbd
Tang, Y.T.
e944297b-6a69-4f74-9d6d-59f0751b3975
Evans, A.G.R.
082f720d-3830-46d7-ba87-b058af733bc3
Norris, D.J.
5491f804-8935-48d9-8a58-18e2c5de777f
Cullis, A.G.
b1bfdce6-de34-4a0b-a239-0c00703bfbea
Paul, D.J.
d16dbdf8-e83a-4629-810b-dd877ce34e34
Robbins, D.J.
a7e1052f-8f34-41dd-b822-ad2bce3fe91b

Olsen, S.H., O’Neill, A.G., Driscoll, L.S., Kwa, K.S.K, Chattopadhyay, S., Waite, A.M., Tang, Y.T., Evans, A.G.R., Norris, D.J., Cullis, A.G., Paul, D.J. and Robbins, D.J. (2003) High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture. IEEE Transactions on Electron Devices, 50 (9), 1961-1969.

Record type: Article

Abstract

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si0.7Ge0.3 on an Si0.85Ge0.15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

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More information

Published date: September 2003
Additional Information: Y.T. Tang, A.M. Waite and A.G.R. Evans were with the Department of Electronics and Computer Science, University of Southampton.
Keywords: CMOS, drain-current enhancement, nMOSFETs, self-heating, SiGe, strained silicon, thermal budget, transconductance enhancement, virtual substrate
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 258987
URI: http://eprints.soton.ac.uk/id/eprint/258987
PURE UUID: 9b65f13a-a293-424f-81eb-4a17b4ba6e8a

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Date deposited: 04 Mar 2004
Last modified: 09 Dec 2019 20:16

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