High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture
High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture
Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si0.7Ge0.3 on an Si0.85Ge0.15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.
CMOS, drain-current enhancement, nMOSFETs, self-heating, SiGe, strained silicon, thermal budget, transconductance enhancement, virtual substrate
1961-1969
Olsen, S.H.
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O’Neill, A.G.
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Driscoll, L.S.
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Kwa, K.S.K
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Chattopadhyay, S.
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Waite, A.M.
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Tang, Y.T.
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Evans, A.G.R.
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Norris, D.J.
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Cullis, A.G.
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Paul, D.J.
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Robbins, D.J.
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September 2003
Olsen, S.H.
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O’Neill, A.G.
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Driscoll, L.S.
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Kwa, K.S.K
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Chattopadhyay, S.
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Waite, A.M.
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Tang, Y.T.
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Evans, A.G.R.
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Norris, D.J.
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Cullis, A.G.
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Paul, D.J.
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Robbins, D.J.
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Olsen, S.H., O’Neill, A.G., Driscoll, L.S., Kwa, K.S.K, Chattopadhyay, S., Waite, A.M., Tang, Y.T., Evans, A.G.R., Norris, D.J., Cullis, A.G., Paul, D.J. and Robbins, D.J.
(2003)
High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture.
IEEE Transactions on Electron Devices, 50 (9), .
Abstract
Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si0.7Ge0.3 on an Si0.85Ge0.15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.
Text
TED_paper_for_K2174s.pdf
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More information
Published date: September 2003
Additional Information:
Y.T. Tang, A.M. Waite and A.G.R. Evans were with the Department of Electronics and Computer Science, University of Southampton.
Keywords:
CMOS, drain-current enhancement, nMOSFETs, self-heating, SiGe, strained silicon, thermal budget, transconductance enhancement, virtual substrate
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 258987
URI: http://eprints.soton.ac.uk/id/eprint/258987
PURE UUID: 9b65f13a-a293-424f-81eb-4a17b4ba6e8a
Catalogue record
Date deposited: 04 Mar 2004
Last modified: 14 Mar 2024 06:17
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Contributors
Author:
S.H. Olsen
Author:
A.G. O’Neill
Author:
L.S. Driscoll
Author:
K.S.K Kwa
Author:
S. Chattopadhyay
Author:
A.M. Waite
Author:
Y.T. Tang
Author:
A.G.R. Evans
Author:
D.J. Norris
Author:
A.G. Cullis
Author:
D.J. Paul
Author:
D.J. Robbins
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