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Behavioral fault modeling and simulation using VHDL-AMS to speed-up analog fault simulation

Kilic, Y and Zwolinski, M (2004) Behavioral fault modeling and simulation using VHDL-AMS to speed-up analog fault simulation Analog Integrated Circuits and Signal Processing, 39, (2), pp. 177-190.

Record type: Article


One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.

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Published date: May 2004
Keywords: behavioural fault modelling macro modelling analogue fault simulation VHDL-AMS
Organisations: EEE


Local EPrints ID: 259464
PURE UUID: b6504dd0-4a4d-48d0-816c-aac20039ad94
ORCID for M Zwolinski: ORCID iD

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Date deposited: 15 Jun 2004
Last modified: 18 Jul 2017 09:23

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Author: Y Kilic
Author: M Zwolinski ORCID iD

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