Recent developments in deca-nanometer vertical MOSFETs
Recent developments in deca-nanometer vertical MOSFETs
We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.
230-235
Hall, S.
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Donaghy, S.
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Buiu, O.
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Gili, E.
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Uchino, T.
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Kunz, V.D.
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de Groot, C.H.
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Ashburn, P.
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2004
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Donaghy, S.
ed32d106-dd25-466d-a4e0-bde4f4c1f09d
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Gili, E.
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Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Kunz, V.D.
c4efd0d1-d850-414d-9c33-12029ac3e060
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hall, S., Donaghy, S., Buiu, O., Gili, E., Uchino, T., Kunz, V.D., de Groot, C.H. and Ashburn, P.
(2004)
Recent developments in deca-nanometer vertical MOSFETs.
Microelectronic Engineering, 72, .
(doi:10.1016/j.mee.2003.12.042).
Abstract
We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.
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Published date: 2004
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 260148
URI: http://eprints.soton.ac.uk/id/eprint/260148
ISSN: 0167-9317
PURE UUID: fdb1b92a-2339-4743-9b04-7893f348cad4
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Date deposited: 25 Nov 2004
Last modified: 15 Mar 2024 03:11
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Contributors
Author:
S. Hall
Author:
S. Donaghy
Author:
O. Buiu
Author:
E. Gili
Author:
T. Uchino
Author:
V.D. Kunz
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